Electro–thermal compact product assemblies including power-electronics modules, embedded controllers, battery interfaces, and dense-pack mechatronic systems have tight coupling between the arrangement of components, connectivity routing topologies, conductive branch geometry, electrical losses, and thermal transport. Existing design procedures typically perform each of these stages in a separated manner. Namely, a possible arrangement of components is first developed, then one of the discrete choices for routing topology is made, and finally geometric refinement takes place. While such strategies make sense in practice, they impose a significant limitation since the routing topology cannot be changed further after starting the physics-based optimization process. Thus, even if the existing routing architecture proves to be inefficient due to high thermal congestion, high Joule losses, or excessive device compaction, the design remains stuck within an inferior routing choice until the design loop starts again. In this work, we propose an approach for solving the electro–thermal routing optimization problem with simultaneous tuning of the topology, device packing, and trace geometry. The candidate branches of the routing graph are represented using relaxable binary variables, while devices and interconnect traces are described by smooth occupancy fields. Graph flow conservation is enforced through graph-flow continuity constraints, electric losses are computed from current-resistive losses, and steady-state thermal transport with boundary convective conditions is considered. The continuation method is used to drive the topology variables towards near-binary values. Comparing our approach with a best-of-many sequentially tuned baseline strategy, we achieve better device compaction, 31.7% decrease in the bounding-box area from 410.4 to 338.2 cm2, 22.6% improvement in the efficiency of trace geometry, 18.7% reduction of interconnect power dissipation from 18.7 to 14.5 W, as well as thermal management efficiency increase by 8.4%, lowering of maximum device temperature from 103.4 to 94.7∘C. The unified approach also avoids multiple restarts of optimization based on individual topology and results in a simpler structure with only eight remaining edges rather than eleven. It is clear from the above observations that topology–geometry co-optimization based on differential equations can offer a significant practical improvement to compact electro-thermal design.